A self-adaptive thermal Interface material with dual-network fixation and confined flow for warped Chip thermal management

Based on the confined flow - dual-network fixation mechanism, a self-adaptive composite phase change material was prepared. • In the chip thermal management, this composite phase change material could reduce the CPU temperature by up to 31.25 °C. • The composite phase change material has self-adaptive capability, reducing the interface thermal resistance by up to 78.56%. With the continuous trend toward high integration, chips are increasingly subjected to high heat-flux densities. However, excessive heat-flux density can induce chip overheating and warpage, increase local interfacial thermal resistance, and ultimately raise the risks of heat-dissipation failure and performance degradation. Therefore, thermal management has become a critical bottleneck restricting the further development of advanced chips, whereas conventional thermal interface materials (TIMs) still struggle to simultaneously accommodate chip warpage and maintain structural stability. To address this challenge, this study proposes a self-adaptive thermal-interface strategy based on a confined-flow and dual-network fixation mechanism. By constructing a calcium chloride tetrahydrate (CaCl 2 ·4H 2 O)/expanded graphite (EG)/in situ-grown silicon carbide nanowire (SiCnws) system, a high-efficiency heat-dissipating composite phase change material (CPCM) was developed, enabling simultaneous warpage conformability and structural stability. When applied to central processing unit (CPU) thermal management, the CPCM achieved a maximum core-temperature reduction of 31.25 °C. After 300 thermal cycles, the maximum fluctuation in the CPU core temperature was only 10.9 °C. Characterization results showed that, upon heating, the CPCM softened and conformed tightly to curved copper sheets, thereby reducing local thermal resistance. Interfacial thermal resistance measurements indicated that the adapted interface exhibited a resistance of 0.215 cm 2 ·K·W −1 , corresponding to a 78.56% reduction relative to the non-adapted state. This study provides a promising technical pathway and theoretical guidance for addressing chip warpage and high-heat-flux dissipation challenges.