Back-interface engineering with patterned micro-nano insulator arrays for high-efficiency kesterite solar cells

Mitigating the open-circuit voltage ( V OC ) deficit caused by non-radiative recombination at the back interface remains a critical challenge for high-performance Cu 2 ZnSn(S,Se) 4 (CZTSSe) solar cells. Conventional passivation using an ultrathin insulating interlayer at the CZTSSe/Mo interface suffers from an inherent trade-off between passivation quality and charge transport. To address this limitation, we introduce a scalable direct-writing inkjet printing technique to construct patterned micro-nano insulator arrays composed of SiO 2 nanoparticles at the back interface. By tailoring the printing parameters to design controllable passivation structures, interface recombination is effectively suppressed while maintaining efficient carrier transport through local openings. As a result, the interface defect density is reduced by 46% and the carrier lifetime is prolonged more than two times. The champion device achieves a remarkable power conversion efficiency (PCE) of 15.03% with an optimal passivation area of 11%. Notably, its V OC deficit is only 253 mV, representing the lowest value among high-performance CZTSSe solar cells. This work provides a novel avenue for interface engineering to suppress non-radiative recombination and demonstrates the potential of inkjet printing technique for advanced contact design in photovoltaics. High-performance CZTSSe solar cell with efficiency exceeding 15% is achieved via back-interface patterned insulator passivation strategy. Optimized back-interface effectively suppresses non-radiative recombination and reduces open-circuit voltage deficits. Download: Download high-res image (154KB) Download: Download full-size image