Trimeric surfactants with high surface activity enable outstanding silicon wafer post-CMP cleaning performance

Silicon wafer cleaning, particularly the removal of nanoparticle contaminants after chemical mechanical polishing (CMP), is critical for advanced semiconductor manufacturing. Ceria (CeO 2 ) nanoparticles are among the most common abrasives in CMP, while their complete removal is challenging due to strong adhesion on the silicon wafer, therefore typically relying on aggressive solutions that may induce surface damage. To address this, the addition of surfactants has been adopted to resolve these challenges. Nonionic surfactants, in particular, have been widely studied due to their good environmental compatibility and low risk of ionic contamination. Herein, we report a class of trimeric nonionic surfactants TBTLn ( n  = 4, 7, 11, and 16), comprising three hydrophobic tert-butyl groups, hydrophilic polyoxyethylene chains, and coordinating imine groups, which exhibit high surface activity and exceptional cleaning performance for CeO 2 nanoparticles. Systematic evaluation reveals that the trimeric architecture endows TBTLn with a remarkably low surface tension and superior wetting capability, significantly outperforming the corresponding monomeric and dimeric surfactants. Notably, TBTL16 with the longest polyoxyethylene chains achieves a perfect particle removal efficiency (PRE) of 100% on silicon substrates at a low concentration of 2 mM. The exceptional PRE is attributed to a synergistic mechanism where superior wetting, interfacial displacement, and coordination collectively act to reduce the adhesion of nanoparticles, enabling complete removal and preventing readsorption, as corroborated by experimental data and theoretical calculations. Collectively, this work presents a series of efficient trimeric surfactants for post-CMP cleaning, with great potential applications in advanced semiconductor manufacturing.